Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

ABSTRACT

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

This patent application is a divisional of U.S. patent application Ser.No. 12/583,743, filed on Aug. 25, 2009, which claims the benefit of U.S.Provisional Patent Application Ser. No. 61/189,960 filed on Aug. 25,2008, which are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

This invention relates to a non-volatile memory cell with Twin MONOSstructure; and more particularly to a non-volatile memory cell with TwinMONOS structure aiming at high reliability, high speed applications.

DESCRIPTION OF THE RELATED ART

Typical binary non-volatile memories have two possible threshold states,with high threshold voltage (Vt) for the logical 0 or OFF cell, and lowVt for the logical 1 or ON cell, as shown in FIG. 1. In order to readthe memory state, a reference level or cell may be utilized, Ref, whichlies mid-way between the two threshold distributions. Typically, a senseamplifier compares two input signals, one is the selected memory cellsignal, and the other is the reference signal, in order to determine thelogical state of the selected cell. The reference signal may be a fixedcurrent signal or a fixed voltage signal or derived from a referencecell, which has characteristics similar to the memory cell. In order toobtain reliable, high speed operation, the reference cell needs to matchthe memory cell characteristics over variations in process conditions,capacitance and other parasitic loading effects, temperature, voltage,program/erase (P/E) cycling and retention conditions, etc.

Generally, nitride or insulator or trap type memories suffer fromthreshold voltage narrowing during cycling and after retention. FIG. 2gives an example of measurement data taken from a Twin MONOS device astaught in U.S. Pat. No. 7,352,033 to Satoh et al, assigned to the sameassignee as the present invention. The graph shows thresholddistributions for program and erase after one million one-shot programand erase cycles 22, and then after high temperature retention bake 24.After the retention bake, window narrowing is observable. Before bake,the window A is 1.5V. After bake, the window B is 0.3V. This windownarrowing is a unique characteristic due to the insulator nature of thestorage medium. Floating gate type memories do not share thischaracteristic because the floating gate is composed of conductivepolysilicon and electrons can move freely within the gate. In insulatoror trap storage, charge is not as mobile, and excess electrons and holescan accumulate in regions within the storage medium. These excess chargebuildups contribute to the instability of the threshold Vt of the memorycell, because over time, or at higher temperatures when hole mobility inthe insulator increases, holes and electrons will recombine, and theoverall threshold Vt of the memory channel will be degraded.Conventionally, at least one reference cell is reserved per erase blockin order to closely track the cycling and retention characteristics ofeach memory block. U.S. Pat. No. 7,352,033 has a MONOS metal bit memoryarray, but the reference is not complementary. Prior art descriptionsusing a memory cell as a reference cell in nitride/trap type memorieshave been described in U.S. Pat. No. 5,954,393 to Perrin, U.S. Pat. No.6,490,204 to Bloom et al, and U.S. Pat. No. 6,584,017 to Maayan et al.These patents describe the challenges of programming and erasing thereference cells. U.S. Pat. No. 7,457,164 to Ohta mentions using tworeference cells having values of 0 and 1 for each word line, but a writeverify operation is required. U.S. Pat. No. 7,471,581 to Tran et alteaches sixteen reference cells per page of memory.

Referring again to FIG. 2, the intermediate reference level is usuallyplaced halfway between the worst-case program and erase thresholdvoltages. Therefore, for single sided conventional sensing of a selectedmemory cell compared against a “half-programmed” reference cell, thesensing threshold margin window is half of the worst case program anderase Vt window.

U.S. Patent Application 20070047307 to Ogura et al, assigned to the sameassignee as the present invention, describes grouping of two adjacentmemory cells into one complementary pair in order to achieve widersignal margins for high speed sensing. In this self-reference scheme, abit of memory data Data<A> consists of two physical complementary bits(A,Ax) that are compared against each other through a sense amplifier orlatch. This self-referencing method provides a highly reliable,straightforward read operation that tracks with temperature, cyclingretention, and memory array parasitics and has a double sensing marginbecause the ON and OFF states are compared against each other instead ofagainst an intermediate reference level, as shown in FIG. 3. FIG. 3shows the program threshold voltage line 31 and the erase thresholdvoltage line 33. The conventional half current/voltage line 35 is shownbetween lines 31 and 33. In the conventional single-sided sensing 37,the cells are compared to the intermediate reference level 35. In thecomplementary pairing double signal window 39, the cells are comparedagainst each other. U.S. Patent Application 2006/0023532 to Hush et alalso describes a method of complementary memory cells. However, thememory is resistive instead of a trap type memory, with an applicationspecifically to replace DRAM, and therefore needs architecture to matchexisting DRAM complementary device architecture.

“N-Channel Complementary Pairing in Nitride Trap Memory” by N. Ogura etal, p. 77-78, NVSMW. 2008, p. 77-78, describes an additional advantagewith a single level self-referencing complementary array is that withsuch improved margins, a simple one-shot Program/Erase scheme may beused without the need for Write verify.

The complementary method described above helps to improve the read andoperation margins. However the additional memory cell size penalty isprohibitive, and runs counter to the industry's trend towards higherdensity.

U.S. Pat. No. 5,523,972 to Rashid et al describes a multi-level (MLC)binary search method of reading and referencing four possible states ina single memory cell, which is also equivalent to storing two bits ofdata in a single cell. FIG. 4 shows the distributions of four differentstates in which each state has a different average threshold voltage,Vt_(—)11, Vt_(—)10, Vt_(—)01, Vt_(—)00. During read, there are threepossible reference voltages, Ref_below lies between the Vt_(—)11 andVt_(—)01 states, Ref center lies between the Vt_(—)10, and Vt_(—)01states, and Ref_above lies between the Vt_(—)01 and Vt_(—)00 states. Inthe binary search method, first the memory cell signal is comparedagainst the center reference cell signal, Ref_center, and then dependingon whether the memory cell threshold is determined to be above or belowthe center reference, the center reference signal is switched for ahigher or lower reference signal level, Ref_above or Ref_below,respectively, to determine the second bit of data. In this way, the fourstates can be distinguished by two successive read sensing operations.This method has two serial reads to determine two bits, but they arecontained in one physical cell, with one cell being compared against themiddle reference first, and then a higher voltage if the output from thefirst read shows a higher VT, or a lower voltage if the output from thefirst read shows a lower VT.

U.S. Pat. No. 7,468,914 to Toda discloses an array of floating gatememory cells that has two reference cells and four levels of data permemory cell.

SUMMARY OF THE INVENTION

It is an object of this invention to describe a complementary referenceoperation method for an insulator or nitride or trap-type storage devicethat provides high reliability, high cycling and high read speed, bygrouping two memory cells into a complementary pair.

It is a further object of this invention to describe a complementaryreference method in which two reference cells are reserved for eacherase block, which provides the same advantages of high reliability andcycling and high read speed, without the area penalty of a two memorycell complementary pair.

It is a still further object to describe a scheme that combines theconcept advantages of complementary with N-bit multi-level storage, sothat reliable read can be performed, even with narrow margins betweenthe 2^(N) threshold voltage levels.

In accordance with the objectives of the invention, a method ofcomplementary pairing of memory cells is achieved. Two physical memorycells are provided in a complementary pair wherein both of the memorycells are in an erased state. An initialization sequence is performed onthe complementary pair to minimize the threshold voltage offset betweenthe two cells in the complementary pair. In order to create acomplementary data value, one of the memory cells in the complementarypair is programmed while the other remains erased. Thereafter, the twocells in the complementary pair are compared with each other using asense amplifier to determine which side is programmed and which side iserased.

Also in accordance with the objectives of the invention, another methodof complementary pairing of memory cells is achieved. A set of tworeference cells per erase block is provided wherein a first referencecell has a value of ‘1’ and a second reference call has a value of ‘0’.A selected memory cell in the erase block is compared to the tworeference cells to determine whether the memory cell has a value of ‘0’or ‘1’.

Also in accordance with the objectives of the invention, another methodof complementary pairing of memory cells is achieved. N bits of data arestored in a complementary pair of memory cells wherein the number oflevels stored in the pair is 2^(N) and wherein the number of level pairgroupings is 2^(N/2).

Also in accordance with the objectives of the invention, a memory cellarray using complementary pairing of memory cells is achieved. Twophysical memory cells are provided in a complementary pair wherein bothof the memory cells are in an erased state. In order to create acomplementary data value, one of the memory cells in the complementarypair is programmed while the other remains erased. A comparator comparesthe two cells in the complementary pair with each other to determinewhich side is programmed and which side is erased.

Also in accordance with the objectives of the invention, another memorycell array using complementary pairing of memory cells is achieved. Anarray of memory cells comprises a set of at least two reference cellsper erase block of memory cells wherein a first reference cell has avalue of ‘1’ and a second reference cell has a value of ‘0’. Acomparator compares a selected memory cell in the erase block to the tworeference cells to determine whether the selected memory cell has avalue of ‘0’ or ‘1’.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIG. 1 describes the threshold distribution windows for the ON and OFFstates in a conventional binary non-volatile memory.

FIG. 2 shows threshold voltage distribution characteristics for atypical Twin MONOS nitride memory before and after 1 million cycles andretention bake.

FIG. 3 describes the double signal sensing window that can be obtainedby the complementary pairing method, described in prior art.

FIG. 4 shows a conventional memory threshold distribution for 2-bit, 4level multi-level storage implementation.

FIG. 5 shows an example of complementary pair grouping in a Twin MONOSNOR array schematic.

FIG. 6 shows the delta Vt distribution for the same data in FIG. 2,after complementary pair grouping.

FIG. 7 shows a state diagram to initialize the complementary pair tomaximize the delta Vt window.

FIG. 8A shows an implementation of 1:1 complementary pair grouping basedon a general non-volatile memory, virtual ground array.

FIG. 8B shows a circuit block diagram for the implementation of FIG. 8A.

FIG. 9A shows an implementation of hybrid X:1 complementary pairgrouping on a general non-volatile memory, virtual ground array.

FIG. 9B shows a first alternative circuit block diagram for theimplementation of FIG. 9A.

FIG. 10 shows a second alternative circuit block diagram for the hybridX:1 complementary pair grouping method.

FIGS. 11A and 11B gives logical equation summaries of the function ofthe comparator and sense amplifier circuits in two alternatives in thehybrid X:1 complementary pair group method.

FIG. 12 shows a third alternative circuit block diagram for the hybridX:1 complementary pair group method.

FIG. 13 shows a fourth alternative circuit block diagram for the hybridX:1 complementary pair group method.

FIG. 14 gives a summary example of the hybrid X:1 complementary pairgroup method.

FIG. 15 shows another variation of the hybrid complementary in a singlelevel bit array.

FIG. 16 shows a threshold distribution for 2-bit multi-level storage.

FIG. 17 shows the read method voltages applied in two steps to sense the2-bit multi-levels.

FIG. 18 shows a threshold distribution for 2-bit multi-level storageafter cycling and retention.

FIG. 19 shows a threshold distribution for 3-bit multi-level storage.

FIG. 20 shows a logical state diagram for sensing the 3-bit multi-levelstorage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be described with reference to the drawing figures,as follows. The first embodiment of the present invention is acomplementary pair grouping that will be described with reference toFIGS. 5, 6, 7, 8A and 8B. The second embodiment of the inventioncomprises a pair of complementary reference cells and will be describedwith reference to FIGS. 9-15. The third embodiment extends complementaryself-referencing to multi-level sensing and is described with referenceto FIGS. 16-20.

FIG. 5 shows a circuit schematic diagram of Twin MONOS memory cellsorganized in a NOR array. It is possible to arrange the memory cells inother types of arrays, such as virtual ground or AND or NAND, etc, but aNOR-type array will be used for this explanation. Two cells M1 and M2are chosen to be a complementary pair. When M1 is programmed, then M2 iserased, and vice versa. The threshold window between M1 and M2 isdefined by delta Vt=Vt(M1)−Vt(M2).

FIG. 6 shows a distribution of delta Vt for the same data from the graphgiven in FIG. 2. Referring back to FIG. 2, the difference between theworst case points in the end-of-life program and erase distributions is0.3V. Given an intermediate reference cell placed halfway within the0.3V, the sensing margin window is about 0.15V. However, when the deltaVt is plotted for the same sample, the worst-case delta Vt C aftercycling and retention is 0.7V. Thus, complementary pairing can providemore than 4× the signal window as by the conventional single-sided read,even without using program and erase verify operations. Program anderase verify are conventional methods employed in order to tighten upthe program and erase threshold distributions and thus improve theworst-case window.

With such a large operation window, program and erase verify operationsare no longer necessary. This circuit simplification can greatly reducethe peripheral logic complexity and area.

The reason for the improvement in the operation window by delta Vt isthat two cells in a complementary pair are highly likely to program anderase at similar speeds, due to their similar physical characteristicsand the statistical nature of nitride trap storage P/E programmechanisms. Of course, it is important to choose two cells that havesimilar channel length and edge effects. For example, due tomisalignment effects, sometimes even-bit addressed cells may havedifferent characteristics than odd-bit address cells. However,differences in physical characteristics with a pair such as channellength variations or unevenness in the film layers, or array edgeeffects, are only one component of the offset threshold voltage.

From data, it has been observed that a major cause of the offsetthreshold voltage in the pair is due to non-physical variations, likeplasma charging effects during wafer processing. Again, this effect is aunique characteristic of nitride or insulator trap type memories. Duringprocessing, high energy electrons can become trapped in the memory cellnitride on a cell-by-cell basis. This type of offset can be removed byimplementing program verify in an initialization sequence. FIG. 7describes an initialization sequence that could be used to reduce theinherent threshold difference between two cells in a complementary pair.First the memory pair is cycled together an N number of times, where Ncan be any number from 0 to about 20, in order to stabilize the P/Eoperations after wafer processing. After that, both memory cells areprogrammed, and the threshold voltages of both memory cells are obtainedthrough a read sweep. If the difference between the memory cellthresholds is greater than a given tolerance, then the memory cell withthe lower Vt is slightly programmed further until the difference betweenthe two cells, or the delta Vt, falls within the acceptable tolerancelevel.

FIGS. 8A and 8B show an implementation of complementary pair groupingbased on a more general type of non-volatile memory, organized in avirtual ground array. The reference cell CELL_X<A> may be located in thedata array as in the prior art embodiment of complementaryself-reference array. The complementary reference may or may not belocated anywhere inside of the data array, so long as the bit lineBLSelected for the selected bit Cell<A> is separate from the bit line.BLSelected_X of the reference bit Cell_X<A>, since the two bit lines arecompared against each other by the sense amplifier 80 in FIG. 8B. Theratio of memory cell to complementary is 1:1, which means that eachcomplementary pair consists of two physical memory cells. During theinitialization process before programming the complementary data, thetwo cells should be near the same value so that when one side isprogrammed, the difference between the two cells can be maximized. Oneside is supposed to be programmed and the other side is supposed to beerased when reading the state that has complementary data. They can becompared either against each other or against another reference cell todetermine what the state is.

FIG. 9 shows an implementation of complementary pair grouping in asecond preferred embodiment of the present invention, which provides thesame advantages of wide window due to delta Vt, without requiring anextra cell per memory cell. The ratio may increase from X:1, dependingon how many cells out of the array are chosen to be reference cells fora corresponding read unit. More cells out of the array may be chosen asreference cells for better matching throughout the array. If thereference cells match the array, it minimizes loss of sense margin dueto differences in array parasitics or differences in devicecharacteristics.

As in the complementary array embodiment, the data cell of unknown state(0 or 1) will be compared against its corresponding reference cell. Inthis embodiment, each reference cell will consist of a known pair ofcomplementary data of both states 0 and 1. A selected cell in the memoryarray will be compared to both states of a complementary reference. Fora binary state read, one of the complementary reference bits will be thecomplement of the read data bit, the other side will be the same stateas the read data bit. Both complementary references may be comparedagainst a bit, resulting in one valid output from the reference sidecomplementary to the selected bit, and the other output from thereference comparison invalid. The valid complementary data will work thesame way as the normal self-reference scheme, with comparison through asense amp or data latch; the margin and tracking will have thosebenefits as with the complementary self-referencing scheme. The validdata will need to be identified and latched, while the invalid data willneed to be identified and then disregarded.

In the preferred embodiment of the invention, there will be at least tworeference cells per erase block. The key feature of the presentinvention is in the sensing method. Usually reference cell thresholdsare parked “halfway” between the program and erase states. In thisinvention, the reference cells are all-the-way programmed or all-the-wayerased. The selected memory cell is compared against both a programmedreference cell and an erased reference cell, and the difference with thesmaller magnitude difference, wins.

The requirements for a valid data side would be for the complementaryreference side which has the greatest difference between the selecteddata bit. That would occur for complementary bits. If the bits were thesame state, the memory cell characteristics would have more similar cellcurrent and voltage. Thus the difference in complementary reference 1,would need to be compared against the difference in complementary 2, andthe output from the pair with the greatest difference should beobtained. In the first embodiment, this could be done by a voltagesubtractor circuit for each pair1 and pair2. The pair with the smallestdifference would be identified, and bit line comparison from that validpair would be sensed and chosen.

FIG. 10 shows another embodiment of this invention; the valid data issimilarly chosen for the largest difference, through two stages of senseamplifiers. The first stage of sensing uses a sense amplifier 101 tocompare the selected bit against each of the two complementary referencecells. The outputs of the two sense amplifiers 101 are then comparedagainst each other in the second stage sense amplifier 103, therebyidentifying the valid reference output with the largest deltavoltage/current. The sense amplifiers used may be either voltage orcurrent sense amplifiers.

FIG. 11A gives a summary of the logical equations that should be appliedby the sense amplifiers for the voltage sensing situation. FIG. 11Bgives a summary of the logical equations that should be applied by thesense amplifiers for the current sensing situation.

FIG. 12 shows that the compare stage can be implemented by voltagesubtraction circuits 121. The sense amplifier 123 compares the outputsof the voltage subtraction circuits 121 to determine the valid referenceoutput.

FIG. 13 shows that the first compare stage can be implemented usingdifferential sense amplifiers 131. Differential sense amplifier 133compares the outputs of the differential sense amplifiers 131 todetermine the valid reference output.

FIG. 14 gives an example of how this complementary referencing methodcould work. In the pre-charge-discharge read sensing method, all bitlines are precharged to around 1.4V, and then the selected memory celland the two reference cells are activated at the same time.

Ref0 is preset to 1.4V and Ref1 is preset to 0.5V. V(B) is the bit linevoltage coupled to the selected memory cell at the time of sensing.V(Ref0) is the bit line voltage coupled to the programmed reference cellat the time of sensing, and it is assumed that the programmed referencecell will have a high threshold voltage, and thus the bit line voltagewill not fall very much. V(Ref1) is the bit line voltage coupled to theerased reference cell at the time of sensing, and it is assumed that theerased reference cell will have a very low threshold voltage, and thusthe bit line voltage will fall the most. The bit line voltages are inputinto a first stage of differential amplifiers 41, and then the outputsof the first stage V(O₀) and V(O₁) are input to a second stagedifferential amplifier 43. In this example, if the output of the secondstate differential amplifier V(O) is less than 0.6V, then the memorycell B is determined to be programmed, otherwise the memory cell B isdetermined to be erased. Four examples are shown in FIG. 14: strongprogrammed 45, weak programmed 46, strong erased 48 and weak erased 49.It is possible to implement the second state differential amplifier withother switch point trigger mechanisms.

The pairing of the reference cell within the memory array needs not belimited to a cell that is immediately adjacent to the selected bit. Formatching array parasitics of capacitance and resistance, however, it isrecommended that the reference cells be near the area of the selectedbits.

The placement of the reference cell within the memory array also helpsto match with each functional unit of memory. While one word line (WL)is read at once, a pair of bit lines (BL's) out of the array could bepotentially chosen as the reference bit line. Since the edge of thearray often has shown the worst characteristics of the memory, the edgeBL's could potentially be used for the complementary reference for therest of the data array.

FIG. 15 shows another variation of the hybrid complementary in thesingle level bit array. In this variation, the memory array is acombination of Complementary bits A and single bit B. A0 is comparedagainst A1. A voltage subtractor compares B against A0 and A1. IfV(A0)−V(B)>V(B)−V(A1), then the smaller subtractor result is discarded.This is a variation of the embodiment where each cell is a complementarypair—some bits are complementary, and some are not.

In another embodiment of this invention, the concept of complementaryself-referencing can be further extended to multi-level sensing. FIG. 16shows a threshold distribution profile for 2-bit or four level memorystorage. The voltages and ranges are given for illustration purposesonly, and should not be construed as limiting in any way. The lowestdistribution a has a maximum threshold voltage of 0V, after cycling andretention, and the second lowest distribution b has a minimum thresholdvoltage of about 0.8V and a maximum threshold voltage of about 1.4V. Thenext threshold distribution c has a minimum threshold voltage of about1.8V and a maximum threshold voltage of about 2.4V. The highestdistribution d has a minimum threshold voltage of 2.7 and a maximumthreshold voltage of about 3.4V. Distributions a and d are stored as apair, and distributions b and c are stored as a pair. Here, one pair isdefined as two memory cells where one memory cell is referred to as“top” and the other memory cell is referred to as “bottom”. The top andbottom cells have corresponding individual top and bottom bit lines, aswell as corresponding individual top and bottom gates. Table 1 shows thebinary data values that can be assigned to each pair grouping.

TABLE 1 Pair Top Vt Bot Vt Value 1 a d 11 d a 00 2 b c 10 c b 01

FIG. 17 shows the method to read in two successive steps. Inpre-charge/discharge read, first both the top and bottom bit lines areprecharged to an intermediate voltage; 0.8V has been chosen for thisexample. The common diffusion between the two memory cells is connectedto a fixed voltage, such as 0V. The outer top and bottom bit lines areconnected to the inputs of a simple differential sense amplifier. InStep 1, the center reference voltage is applied to the gates of the topand bottom cells, in order to determine which of the two memory gateshas the higher threshold voltage. If the top threshold voltage is higherthan the bottom threshold voltage, than the voltages in Step 2 b areapplied to the control gates, otherwise Step 2 a is used. In this way,the data within the complementary pair can be determined. In Step 2, thegates have different voltages, 0.5 and 2.5, applied, and the bit lineoutputs on the top and bottom gates are complementary ˜0.8V, ˜0V.

As in single level complementary referencing, Step 1 compares the stateof complementary data between the top and bottom devices. The read canbe as described earlier comparing against each other, or comparing eachbit against a reference. This data is stored as the first bit of data,and the second step commences to see if the complementary data is a widemargin level pair 2 data or small level 1 pair data (FIG. 18). Theoutput of this second step gives the second bit of data in the 2 bitmulti-level data. The sense method is similar to that of the first step,however the low gate voltages (Ex: ˜0.5V) between the low voltage valuesof level pair 2 and level pair 1, is applied to the side that isdetermined to be low from Step 1. Simultaneously, the high gate voltage(Ex; ˜2.5V) between the high voltage values of level pair 2 and levelpair 1, is applied to the side that is determined to be high from Step1. The complementary data from the top and bottom cells are comparedagainst each other, giving the second bit of data. The pair 2 bit/2cells, would have a net result of 1 bit/cell, which would improve thepenalty of doubling of area for regular complementary array.

In FIG. 17, only the memory gates have been drawn, but it is alsopossible to add a separate select gate within the memory cell. It ispossible to read the memory cell in both the forward and the reversedirections, but reversing the biases of the source and drains. Forexample, the common diffusion voltage can be fixed to 0.8V instead of0V, and the top and bottom bit lines could be precharged to 0V, insteadof 0.8V. Furthermore, the pre-charge/discharge sensing method is shownhere for illustration, but it is also possible to extend this approachto other read methods such as source-follower or current sensing.

This multi-level complementary method provides a very reliable read,even if the threshold voltages shift with cycling and retention. FIG. 18shows an example of how the positive threshold voltages may shift downwith cycling retention while the negative threshold voltages might shiftup with cycling and retention (shown by dashed lines). In this extremeillustration, even if the threshold voltages were to shift past theactual reference levels, because sensing operations are performedrelative to each other, the read value would still output correctly.Generally, for conventional multi-level implemented by a single-sidedselect, if one threshold voltage level shifts, then the read will outputincorrectly, or the reference cells will also need to be recalibrated insome way. Here, it is possible to keep using the same reference levels,which simplifies the reference circuits and peripheral logic.

FIG. 19 shows how 3 bits of data could be stored in a singlecomplementary pair. Eight levels are grouped into 4 pairs, and the readwould be performed in 3 successive steps. The logical state diagram isgiven in FIG. 20.

In the complementary multi-level method of the invention, the data iscomplementary and the complementary data is compared against itself, inthe first and second steps. The first step determines which cell ishigher, and then the second step determines if the high cell is abovethe higher VT, and if the low cell is below the lowest VT. Themulti-level complementary helps improve the area density to that ofnon-complementary single level data, while having the benefits of a wellmatched, tracking with cycling, self-referenced data.

Program of the distributions for multi-level complementary can becontrolled by factors of time, or number of pulses, or control gatevoltage or drain voltage, as well as current. It is recommended that,especially for multi-level complementary, the initial delta Vt betweenthe two cells in a pair be as close to 0 as possible, either by carefulprogramming, or by choosing the physical pair groups to best match theVt characteristics, or by minimizing or matching the plasma chargingduring processing.

The present invention comprises three embodiments: two memory cells in aphysical complementary pair, a complementary pair of reference cells foreach erase block, and a physical complementary pair storing multipledata bits. The present invention addresses retention loss for greatersensing margin and faster read, especially for trap-type memories.

What is claimed is:
 1. A method of complementary pairing of memory cellscomprising: providing a set of at least two reference cells per eraseblock wherein a first reference cell has a value of ‘1’ and a secondreference cell has a value of ‘0’; and comparing a selected memory cellin said erase block to said two reference cells to determine whethersaid memory cell has a value of ‘0’ or ‘1’.
 2. The method according toclaim 1 wherein said comparing is performed by a sense amplifier whereinsaid sense amplifier performs a subtraction-like function in order todetermine whether said selected memory cell's signal is closer to saidfirst or second reference signal.
 3. The method according to claim 1wherein said comparing is performed by a data latch wherein said datalatch performs a subtraction-like function in order to determine whethersaid selected memory cell's signal is closer to said first or secondreference signal.
 4. The method according to claim 3 wherein saidsubtraction-like function is performed by a voltage subtractor circuit.5. The method according to claim 1 wherein: a first sense amplifiercompares said selected memory cell to said first reference cell; asecond sense amplifier compares said selected memory cell to said secondreference cell; and a third sense amplifier compares outputs from saidfirst and second sense amplifiers to each other to find the output withthe largest delta voltage or current.
 6. The method according to claim 5wherein said first, second, and third sense amplifiers are voltage senseamplifiers or current sense amplifiers.
 7. The method according to claim1 wherein: a first voltage subtractor compares said selected memory cellto said first reference cell; a second voltage subtractor compares saidselected memory cell to said second reference cell; and a senseamplifier compares outputs from said first and second subtractors toeach other to find the output with the largest delta signal.
 8. Themethod according to claim 1 comprising: precharging all bit lines afirst voltage; presetting said first reference cell to said firstvoltage and presetting said second reference cell to a second voltagelower than said first voltage; thereafter activating said selectedmemory cell and said first and second reference cells simultaneously;thereafter sensing bit line voltages from said selected memory cell andsaid first and second reference cells; inputting bit line voltages ofsaid first reference cell and said selected memory cell into a firstdifferential amplifier; inputting bit line voltages of said secondreference cell and said selected memory cell into a second differentialamplifier; and thereafter inputting outputs of said first and seconddifferential amplifiers into a third differential amplifier to determineif said memory cell is programmed or erased.
 9. A memory cell arraycomprising: an array of insulator or nitride or trap-type storage devicememory cells; a set of two reference cells per erase block of memorycells wherein a first reference cell has a value of ‘1’ and a secondreference cell has a value of ‘0’; and a comparator comparing a selectedmemory cell in said erase block to said two reference cells to determinewhether said memory cell has a value of ‘0’ or ‘1’.
 10. The memory cellarray according to claim 9 wherein said comparator is a sense amplifieror a data latch performing a subtraction-like function in order todetermine whether said selected memory cell's threshold voltage iscloser to said first or second reference cell.
 11. The memory cell arrayaccording to claim 9 wherein said comparator is a sense amplifier or adata latch performing a subtraction-like function in order to determinewhether said selected memory cell's current is closer to said first orsecond reference cell.
 12. The memory cell array according to claim 9wherein said comparator comprises: a first sense amplifier comparingsaid selected memory cell to said first reference cell; a second senseamplifier comparing said selected memory cell to said second referencecell; and a third sense amplifier comparing outputs from said first andsecond sense amplifiers to each other to find the output with thelargest delta voltage or current.